Senior ASIC Design Engineer — Edge AI Vision SoCs

Ambarella; Headquarters (ID); Vor Ort; USD 195.000 - 226.000; Vollzeit

Benefits dieser Stelle

RSU grants

Annual RSU grants

Competitive benefits

Zusammenfassung

Ambarella is seeking an experienced VLSI designer to work on next-generation edge AI SoCs, spanning video compression, image processing, and flexible compute architectures. You will influence micro-architecture, optimize RTL for performance, power, and area, and participate in chip bring-up from concept to silicon.

The role requires a Master’s degree and 5–10 years of relevant experience, with strong SystemVerilog/Verilog and scripting skills (Python, Perl).

Qualifikationen

• Master’s degree in electrical/electronics/computer engineering with 5–10 years of experience.
• Strong knowledge of SystemVerilog/Verilog; Python and Perl scripting.
• Experience in design verification and functional coverage; assembly language familiarity.
• Good communication, team player, and problem-solving skills; timing closure knowledge is a plus.

Aufgaben

• Design and implement video compression, image processing and AI-focused compute systems in SystemVerilog.
• Synthesize and optimize RTL for timing, area, and power; verify with code coverage.
• Develop front-end methodologies and tool flows; participate in chip bring-up and testing.

Kenntnisse

SystemVerilog

Verilog

Python

Perl

VLSI design

Computer architecture

Logic design

RTL verification

Timing closure

Ausbildung

Master's degree in Electrical/Electronics/Computer Engineering

Jobbeschreibung

Ambarella is seeking an experienced VLSI designer to work on next-generation edge AI SoCs, spanning video compression, image processing, and flexible compute architectures. You will influence micro-architecture, optimize RTL for performance, power, and area, and participate in chip bring-up from concept to silicon.

The role requires a Master’s degree and 5–10 years of relevant experience, with strong SystemVerilog/Verilog and scripting skills (Python, Perl).