ASIC Engineer, Design [University Grad]

Anysilicon; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Meta is seeking ASIC Design Engineers to join its Infrastructure organization, focusing on the development of advanced ASICs for applications in machine learning, video transcoding, and network acceleration. You will work with cross-functional teams to ensure robust timing and power-aware designs.

The role requires a Bachelor's degree (or PhD) in a related field and a strong background in RTL/HDL design. Relocation and full-time commitment are typical for this position.

Qualifications

• Experience in micro-architecture and RTL development for complex control and data path IPs.
• Proficiency in RTL development using Verilog, SystemVerilog, and HLS.

Responsibilities

• Conduct architecture exploration and micro-architecture development.
• Identify, select, and integrate soft and hard IP components.
• Collaborate with verification and emulation teams to develop test plans and debug issues.
• Work with the implementation team to finalize designs concerning timing and power constraints.

Skills

RTL development

micro-architecture

Verilog

SystemVerilog

HLS

Education

Bachelor’s degree in CS/CE

PhD in CS/CE

Job description

Meta is seeking ASIC Design Engineers to join its Infrastructure organization, focusing on the development of advanced ASICs for applications in machine learning, video transcoding, and network acceleration. This role involves collaboration across various teams to ensure the successful design and implementation of cutting-edge technology.

Responsibilities:

• Conduct architecture exploration and micro-architecture development.
• Identify, select, and integrate soft and hard IP components.
• Collaborate with verification and emulation teams to develop test plans and debug issues.
• Work with the implementation team to finalize designs concerning timing and power constraints.

Qualifications:

• Currently pursuing or holding a Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, with completion required before joining Meta.
• Currently pursuing or holding a PhD in Computer Science, Computer Engineering, or a relevant technical field.

Skills:

• Experience in micro-architecture and RTL development for complex control and data path IPs.
• Proficiency in RTL development using Verilog, SystemVerilog, and HLS.

Work Email

Free No obligation Response within 24 hours