Senior ASIC Design Engineer - High-Speed Optics

Celero Communications, Inc.; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications in Irvine, CA is seeking an experienced ASIC Design Engineer to develop high-speed digital ASICs for optical communication systems. You will own RTL development, verification, and integration across DSP, SerDes, and mixed-signal blocks.

The role requires strong Verilog/SystemVerilog skills, deep RTL fundamentals, and hands-on experience with modern ASIC flows and EDA tools, in a fast-paced startup environment.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of digital ASIC design experience with ownership of complex blocks or subsystems.
• Proficiency in Verilog and SystemVerilog.
• Strong RTL design fundamentals and ASIC development methodologies.
• Hands-on experience with ASIC design flows and industry-standard EDA tools.
• Knowledge of DSP, high-speed SerDes, analog/mixed-signal interactions, and optical communications.

Responsibilities

• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
• Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop mixed-signal ASICs.
• Work on high-speed data paths, signal processing blocks, and interfaces for optical systems.
• Perform synthesis, timing analysis, lint, formal equivalence, CDC, and related signoff activities.
• Optimize designs for performance, power, and area (PPA).
• Conduct RTL simulation and debugging to ensure functionality and performance.

Skills

Verilog/SystemVerilog

DSP

SerDes

RTL design

Synthesis

Timing analysis

Python/Tcl scripting

Cross-functional collaboration

Digital ASIC design

EDA tools

Education

B.S. in Electrical/Computer Engineering or related

Tools

EDA tool flows

Job description

Celero Communications in Irvine, CA is seeking an experienced ASIC Design Engineer to develop high-speed digital ASICs for optical communication systems. You will own RTL development, verification, and integration across DSP, SerDes, and mixed-signal blocks.

The role requires strong Verilog/SystemVerilog skills, deep RTL fundamentals, and hands-on experience with modern ASIC flows and EDA tools, in a fast-paced startup environment.