Senior ASIC Design Engineer - Optical & High-Speed DSP

Celero Communications; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications is seeking an ASIC Design Engineer to develop high-speed digital ASICs for optical communications and data center infrastructure. You will lead RTL design, verification, and integration with DSP, SerDes, and mixed-signal blocks.

The role requires strong Verilog/SystemVerilog expertise, 5+ years in digital ASIC design, and collaboration across multiple engineering teams in a fast-paced startup environment. Competitive US base salary is offered.

Qualifications

• Bachelor's or higher in Electrical Engineering or Computer Engineering.
• 5+ years in digital ASIC design with ownership of complex blocks.
• Proficient in Verilog/SystemVerilog.
• Experience with DSP, SerDes, and mixed-signal interfaces.
• Familiar with EDA tool flows and ASIC development methodologies.

Responsibilities

• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
• Develop DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to integrate mixed-signal ASICs.
• Develop high-speed data paths, signal processing blocks, and interfaces for optical systems.
• Perform synthesis, timing, lint, CDC, and related ASIC implementation and signoff activities.
• Optimize designs for performance, power, and area (PPA).
• Conduct RTL simulation and debugging to ensure functionality and performance.
• Contribute to block-level and top-level integration, verification, and silicon bring-up.
• Participate in architecture and design reviews and provide technical guidance.

Skills

Verilog/SystemVerilog

DSP

SerDes

Mixed-Signal ICs

Digital communications

Optical communications

Synthesis/STA/CDC

Education

Bachelor's or higher in EE/CE

Job description

Celero Communications is seeking an ASIC Design Engineer to develop high-speed digital ASICs for optical communications and data center infrastructure. You will lead RTL design, verification, and integration with DSP, SerDes, and mixed-signal blocks.

The role requires strong Verilog/SystemVerilog expertise, 5+ years in digital ASIC design, and collaboration across multiple engineering teams in a fast-paced startup environment. Competitive US base salary is offered.