Senior ASIC Design Engineer - DSP/SerDes for Optical Tech

Socket.dev; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications is seeking an experienced ASIC Design Engineer to advance high-speed optical ASICs. You will own DSP, SerDes, and mixed-signal integration across RTL and verification, closely collaborating with Analog, Verification, and Physical Design teams.

The role emphasizes architecture-to-tapeout involvement, with emphasis on PPA optimization, RTL simulation, and scripting to automate design tasks. This is a high-impact startup environment in the US.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in digital ASIC design with ownership of complex blocks/subsystems.
• Strong proficiency in Verilog and/or SystemVerilog.
• Strong understanding of digital design principles, RTL design, and ASIC development methodologies.
• Hands-on experience with ASIC design flows and industry-standard EDA tools.
• Familiarity with verification like UVM and/or formal verification.

Responsibilities

• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
• Develop and integrate DSP, digital communication, and high-speed SerDes functionality into ASIC designs.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to integrate mixed-signal ASICs.
• Design and develop high-speed data paths, signal processing blocks, control logic, and interfaces for optical systems.
• Perform synthesis, timing analysis, lint, formal equivalence, CDC, and related signoff activities.
• Optimize designs for performance, power, and area (PPA).
• Perform RTL simulation and debugging to ensure functionality and performance.
• Contribute to block-level/top-level integration, verification, and silicon bring-up.
• Participate in architecture/design reviews and provide technical guidance to engineers.
• Collaborate with cross-functional teams to troubleshoot design and system issues.
• Develop scripts and automation using Python, Tcl, or similar languages.
• Contribute to ASIC development from architecture/RTL through tapeout and silicon validation.

Skills

Verilog/SystemVerilog

RTL design

ASIC design flows

Python scripting

Formal verification / UVM

Problem solving

Education

Bachelor’s or higher in Electrical/Computer Engineering

Tools

MATLAB

Python

Tcl

Job description

Celero Communications is seeking an experienced ASIC Design Engineer to advance high-speed optical ASICs. You will own DSP, SerDes, and mixed-signal integration across RTL and verification, closely collaborating with Analog, Verification, and Physical Design teams.

The role emphasizes architecture-to-tapeout involvement, with emphasis on PPA optimization, RTL simulation, and scripting to automate design tasks. This is a high-impact startup environment in the US.