Senior ASIC Design Engineer - Co-Packaged Optics

Ayar Labs; San Jose (CA); On-site; USD 180,000 - 223,000; Full time

Job summary

A pioneering technology company located in San Jose is seeking an experienced ASIC Sr. Staff Engineer to design and debug complex digital subsystems. The ideal candidate should have a strong background in digital design, specifically with Verilog and SystemVerilog, along with expertise in ASIC verification. This role involves collaborative development of algorithm specifications and hands-on work with high-speed optical systems. Competitive salary range from $180,000 to $223,000 is offered, while promoting a diverse and inclusive workplace.

Qualifications

• 5+ years of experience in ASIC design.
• Mastery of Verilog and SystemVerilog for RTL design and verification.
• Proficiency in ASIC verification tools and Python programming.

Responsibilities

• Develop detailed digital algorithm specifications.
• Optimize RTL in Verilog for complex electro-optical ASICs.
• Bring-up and debug of in-house custom silicon.

Skills

Verilog

SystemVerilog

ASIC design

Python

C

C++

ASIC verification tools

Digital design

Education

BS or MS in Electrical Engineering or Computer Engineering

Tools

Xcelium

VCS

Questa

Genus

Design Compiler

Job description

A pioneering technology company located in San Jose is seeking an experienced ASIC Sr. Staff Engineer to design and debug complex digital subsystems. The ideal candidate should have a strong background in digital design, specifically with Verilog and SystemVerilog, along with expertise in ASIC verification. This role involves collaborative development of algorithm specifications and hands-on work with high-speed optical systems. Competitive salary range from $180,000 to $223,000 is offered, while promoting a diverse and inclusive workplace.