ML Acceleration ASIC Design Engineer

Amazon; Austin (TX); On-site; USD 136,000 - 184,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Amazon in Austin, TX is seeking an ASIC Design Engineer to design and optimize high-performance hardware for AWS Inferentia and datacenter servers. You will craft SystemVerilog RTL, run synthesis, and validate timing while balancing power, area, and performance.

Collaborate with architects, verification, and backend teams to deliver robust designs and meet project goals, while upholding Amazon's leadership principles and a culture of inclusion.

Qualifications

• Bachelor's degree or equivalent.
• 3+ years of non-internship design or architecture experience.
• Master's degree in computer science or equivalent is preferred.
• 3+ years of full software development life cycle experience (coding standards, reviews, SCM, build, testing, operations) preferred.

Responsibilities

• Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets.
• Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements.
• Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints.
• Execute lint and clock domain crossing quality checks to ensure design integrity.
• Collaborate closely with cross-functional teams including architects, designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts

Skills

RTL design

SystemVerilog

Synthesis

Timing analysis

Cross-functional collaboration

Education

Bachelor's degree or equivalent

Master's degree in CS or equivalent

Job description

Amazon in Austin, TX is seeking an ASIC Design Engineer to design and optimize high-performance hardware for AWS Inferentia and datacenter servers. You will craft SystemVerilog RTL, run synthesis, and validate timing while balancing power, area, and performance.

Collaborate with architects, verification, and backend teams to deliver robust designs and meet project goals, while upholding Amazon's leadership principles and a culture of inclusion.