Senior ASIC Design Engineer – DSP/SerDes for Optical Systems

Anysilicon; San Jose (CA); Sur place; USD 190 000 - 270 000; Plein temps

Résumé du poste

Celero Communications seeks a Senior ASIC Design Engineer to develop advanced ASICs for high-speed optical communication systems. You will design high-performance digital circuits and collaborate with DSP, Analog, and SerDes teams to integrate complex functionality.

Responsibilities include RTL design, synthesis, timing analysis, CDC, and PPA optimization, with opportunities to lead architecture, verification, and silicon bring-up while creating automation scripts in Python or Tcl.

Qualifications

• Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• 10 years of experience in digital ASIC design with ownership of complex ASIC blocks or subsystems.
• Strong proficiency in Verilog and/or SystemVerilog.
• Understanding of digital design principles, RTL design, and ASIC development methodologies.
• Hands-on experience with ASIC design flows and industry-standard EDA tools.

Responsabilités

• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
• Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop mixed-signal ASICs.
• Participate in the design and development of high-speed data paths, signal processing blocks, control logic, and interfaces for optical communication systems.
• Perform synthesis, timing analysis, lint, formal equivalence, and Clock Domain Crossing (CDC) activities.
• Optimize designs for performance, power, and area (PPA).
• Conduct RTL simulation and debugging to ensure design functionality and performance.
• Contribute to block-level and top-level integration, verification, and silicon bring-up.
• Participate in architecture and design reviews and provide technical guidance to other engineers.
• Develop scripts and automation using Python, Tcl, or similar languages to improve design and verification efficiency.

Connaissances

DSP

SerDes

Verilog

SystemVerilog

RTL design

EDA tools

Python scripting

Digital design

Formation

Master's or Ph.D. in Electrical Engineering or related field

Outils

Industry-standard EDA tools

Description du poste

Celero Communications seeks a Senior ASIC Design Engineer to develop advanced ASICs for high-speed optical communication systems. You will design high-performance digital circuits and collaborate with DSP, Analog, and SerDes teams to integrate complex functionality.

Responsibilities include RTL design, synthesis, timing analysis, CDC, and PPA optimization, with opportunities to lead architecture, verification, and silicon bring-up while creating automation scripts in Python or Tcl.