Senior ASIC Design Engineer - DFX

Nvidia Corporation; Santa Clara (CA); On-site; USD 168,000 - 310,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior ASIC Design Engineer – DFX to lead fuse controller and DFT IP architecture for cutting-edge SoCs. You will develop scalable DFT methods and collaborate with architects, platform, and software teams to define feature sets.

You will mentor junior engineers, support post-silicon bring-up, and contribute to test plans and validation. The role rewards deep technical curiosity, teamwork, and solving complex challenges in a fast-paced semiconductor environment.

Qualifications

• 8+ years in SoC architecture, RTL design, and verification
• 5+ years of hands-on SoC architecture, RTL design and verification
• Proficiency in Verilog; UVM experience a plus
• Deep expertise in DFT design, methodology, and implementation
• Familiarity with clocking, STA, placement & routing, and power optimization
• Post-silicon bring-up on ATE, pattern formats, test program development, failure analysis
• Python, Perl, and Tcl scripting proficiency
• Excellent communication and collaborative mindset

Responsibilities

• Own the architecture and design of fuse controller and other DFT IPs for SoCs
• Develop, deploy, and enhance DFT methodologies for scalability
• Define and align feature sets with architects, platform, and software teams
• Partner with design, verification, synthesis, timing, and backend teams for cohesive integration
• Create and execute test plans for functional and full-chip DFT verification
• Support post-silicon bring-up and validation including debugging
• Mentor junior engineers on test design strategies and trade-offs

Skills

Verilog RTL

Python scripting

DFT methodology

SoC architecture

Communication skills

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

UVM

Tcl scripting

Perl scripting

Job description

Senior ASIC Design Engineer – DFX

We are now looking for a Senior ASIC Design Engineer – DFX! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI— the next era of computing. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today. Design‑for‑Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post‑silicon validation on some of the industry’s most complex semiconductor chips.

What You’ll Be Doing

• Own the architecture and design of fuse controller and other DFT IPs for cutting‑edge SoC designs.
• Develop, deploy, and enhance DFT methodologies for scalability and future product needs.
• Define and align feature sets by working closely with architects, platform, and software teams.
• Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.
• Create and execute test plans to support both functional and DFT full‑chip verification.
• Support post‑silicon bring‑up and validation efforts including debug and issue resolution.
• Mentor junior engineers on test design strategies and trade‑offs related to cost, quality, and performance.

What We Need to See

• Bachelors degree (or equivalent experience) with 8+ years of experience, or Master’s degree in Electrical Engineering or related field with 6+ years experience.
• 5+ years of hands‑on experience in SoC architecture, RTL design, and verification.
• Strong proficiency in micro‑architecture and RTL development using Verilog. (UVM experience is a plus.)
• Deep expertise in DFT design, methodology, and implementation.
• Familiarity with related domains such as clocking, STA, place & route, and power optimization.
• Experience in post‑silicon bring‑up on ATE, including understanding of pattern formats, test program development, and failure analysis.
• Proficiency in scripting languages such as Python, Perl, or Tcl.
• Excellent communication skills and a collaborative mindset — with a curiosity and passion for solving complex technical challenges.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000USD–264,500USD for Level4, and 196,000USD–310,500USD for Level5. You will also be eligible for equity and benefits.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.