Senior ASIC Design Engineer - Data Center SOC

ScaleFlux; Milpitas (CA); On-site; USD 160,000 - 210,000; Full time

Job summary

ScaleFlux in San Jose, California, is seeking a Sr. ASIC Design Engineer to join our expanding team focused on high-performance data center infrastructure ASIC design and SOC development.

You will develop RTL in Verilog/SystemVerilog, work on NAND memory controllers, and collaborate with customers to validate designs and deliver timely, high-quality results for enterprise-scale systems. This role requires strong debugging skills, clear communication, and the ability to work across

Qualifications

• MS degree required in Electrical or Computer Engineering.
• Proven experience with Verilog and SystemVerilog.
• Experience with NAND memory interfaces is a plus.

Responsibilities

• Develop advanced NAND memory controller with managed power and performance
• IP and/or chip level micro-architectures, implementation, and validation
• Write up micro-architecture and design document and be able to present to customers
• Develop RTL, perform synthesis, lint and CDC check
• Working with customers to trouble shooting, debug, and tune system performance

Skills

Verilog

SystemVerilog

C programming

Communication skills

Teamwork

Memory controller

Education

MS in Electrical Engineering or Computer Engineering

Job description

ScaleFlux in San Jose, California, is seeking a Sr. ASIC Design Engineer to join our expanding team focused on high-performance data center infrastructure ASIC design and SOC development.

You will develop RTL in Verilog/SystemVerilog, work on NAND memory controllers, and collaborate with customers to validate designs and deliver timely, high-quality results for enterprise-scale systems. This role requires strong debugging skills, clear communication, and the ability to work across