Senior ASIC Design Engineer – RTL, Verification, Bring-Up

Palo Alto Networks; California; On-site; USD 156,000 - 253,000; Full time

Job summary

Palo Alto Networks is seeking an experienced ASIC design lead to own front-end design and RTL development for next-generation firewall platforms. You will collaborate with verification, physical design, and silicon bring-up teams to meet aggressive performance, power, and schedule goals.

The role requires deep expertise in micro-architecture, datapath design, and rigorous debugging across stages, with opportunities to apply AI-driven design flows to reduce risk and accelerate delivery.

Qualifications

• BS in EE, CE, or CS (MSEE or equivalent military experience preferred).
• 10+ years’ front-end ASIC design ownership, shipping 2+ chips to mass production.
• Expert SystemVerilog RTL skills.
• Proven track record of selecting, integrating, and configuring complex IP blocks for high-speed interfaces such as PCIe, Ethernet, or DDR.
• Scripting proficiency (Python, C/C++, Perl, bash or tcsh).
• Defining micro-architecture from high-level requirements; datapath design for intricate digital logic; debugging across simulation, emulation, and silicon.
• Analyzing timing, power, and area reports and driving fixes.
• Excellent leadership, collaboration, and written/verbal communication.

Responsibilities

• Write clear design and micro-architecture specifications.
• Design SystemVerilog RTL that meets area, performance, and power targets.
• Verify your blocks with simulation, emulation, formal methods, and silicon bring-up.
• Collaborate with verification engineers to debug scenarios and close coverage.
• Partner with physical-design teams to review reports and rewrite RTL to close critical paths.
• Innovate by piloting AI-driven design or verification flows to cut schedule risk.

Skills

SystemVerilog RTL

ASIC design ownership

Datapath design

Timing/power/area analysis

Python

C/C++

Leadership / communication

Education

BS in EE/CE/CS

MSEE or equivalent military experience preferred

Tools

Python

C/C++

Perl

bash

Job description

Palo Alto Networks is seeking an experienced ASIC design lead to own front-end design and RTL development for next-generation firewall platforms. You will collaborate with verification, physical design, and silicon bring-up teams to meet aggressive performance, power, and schedule goals.

The role requires deep expertise in micro-architecture, datapath design, and rigorous debugging across stages, with opportunities to apply AI-driven design flows to reduce risk and accelerate delivery.