Senior ASIC Design Architect (12nm) – RTL & Mentorship

AGL Technologies Inc.; City of Utica (NY); On-site; USD 140,000 - 230,000; Full time

Job summary

AGL Technologies Inc. is seeking an experienced Senior ASIC Design Engineer to drive architecture, RTL implementation, and physical design strategy for an advanced 12nm ASIC. You will lead top-level blocks and mentor junior block owners through RTL execution and physical realization.

Responsibilities include collaboration on timing closure, floorplanning, and power optimization, along with owning HDL development and verification activities to ensure high coverage and robust silicon.

Qualifications

• 8+ years of hands-on ASIC design and architecture experience.
• US citizenship is required.
• Experience with 12nm FinFET or lower is preferred.
• Proficient in VHDL for synthesizable RTL.
• Familiar with Cadence toolchain: synthesis, STA, linting, CDC, power analysis.

Responsibilities

• Define top-level architecture and specs with technical leadership.
• Lead RTL development for critical IP blocks through design freeze.
• Collaborate on 12nm floorplanning, synthesis, timing closure, and power optimization.
• Mentor junior/mid-level engineers and review code.
• Support testbench architecture and verification with high coverage.

Skills

Architecture design

RTL development

Physical design

Mentorship

Design verification

Tools

Cadence tools

VHDL

Job description

AGL Technologies Inc. is seeking an experienced Senior ASIC Design Engineer to drive architecture, RTL implementation, and physical design strategy for an advanced 12nm ASIC. You will lead top-level blocks and mentor junior block owners through RTL execution and physical realization.

Responsibilities include collaboration on timing closure, floorplanning, and power optimization, along with owning HDL development and verification activities to ensure high coverage and robust silicon.