Senior ASIC Design Engineer - RTL & EDA Expert

Advanced Micro Devices, Inc.; San Jose (CA); Presencial; USD 120.000 - 180.000; Tempo integral

Benefícios oferecidos por esta vaga

AMD benefits at a glance

Resumo da vaga

Advanced Micro Devices, Inc. (Xilinx, Inc. subsidiary) is seeking a Sr. Silicon Design Engineer to research, design, verify, and test ASIC-oriented components for advanced semiconductor devices in a fast-paced environment.

The role involves defining architectures, simulating modules, and analyzing timing across flat and hierarchical flows, with expertise in RTL quality checks, EDA tools, and TCL scripting. Travel is not required.

Qualificações

• Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or related field.
• One (1) year of experience in the job offered or a closely related engineering role.
• Experience with RTL quality checks, timing constraints, and timing analysis.
• Proficiency with EDA tools such as Synopsys Design Compiler, PrimeTime, SpyGlass and FishTail.
• Ability to script in TCL within EDA environments and Linux TCL shells.

Responsabilidades

• Research, design, develop, and/or test electronic components and systems for semiconductor manufacturing.
• Oversee definition, design, verification, and documentation for ASIC development.
• Define module interfaces for simulation and contribute to multidimensional IC designs.
• Evaluate the design flow from high-level designs to synthesis, place and route, and timing/power use.

Conhecimentos

RTL checks

Timing constraints

Timing analysis

EDA tools

TCL scripting

Formação

Master's degree in Computer/Electrical/Electronics Engineering

Ferramentas

Synopsys Design Compiler

PrimeTime

SpyGlass

FishTail

Descrição da vaga

Advanced Micro Devices, Inc. (Xilinx, Inc. subsidiary) is seeking a Sr. Silicon Design Engineer to research, design, verify, and test ASIC-oriented components for advanced semiconductor devices in a fast-paced environment.

The role involves defining architectures, simulating modules, and analyzing timing across flat and hierarchical flows, with expertise in RTL quality checks, EDA tools, and TCL scripting. Travel is not required.