Senior ASIC Design Engineer

AGL Technologies Inc.; City of Utica (NY); On-site; USD 140,000 - 230,000; Full time

Job summary

AGL Technologies Inc. is seeking an experienced Senior ASIC Design Engineer to drive architecture, RTL implementation, and physical design strategy for an advanced 12nm ASIC. You will lead top-level blocks and mentor junior block owners through RTL execution and physical realization.

Responsibilities include collaboration on timing closure, floorplanning, and power optimization, along with owning HDL development and verification activities to ensure high coverage and robust silicon.

Qualifications

• 8+ years of hands-on ASIC design and architecture experience.
• US citizenship is required.
• Experience with 12nm FinFET or lower is preferred.
• Proficient in VHDL for synthesizable RTL.
• Familiar with Cadence toolchain: synthesis, STA, linting, CDC, power analysis.

Responsibilities

• Define top-level architecture and specs with technical leadership.
• Lead RTL development for critical IP blocks through design freeze.
• Collaborate on 12nm floorplanning, synthesis, timing closure, and power optimization.
• Mentor junior/mid-level engineers and review code.
• Support testbench architecture and verification with high coverage.

Skills

Architecture design

RTL development

Physical design

Mentorship

Design verification

Tools

Cadence tools

VHDL

Job description

We are seeking an experienced Senior ASIC Design Engineer to drive the architecture, RTL implementation, and physical design strategy for an advanced, cyber-resilient 12nm ASIC. In this role, you will design critical top-level blocks and play a central mentorship role, guiding junior and mid-level block owners through RTL execution and physical realization.

Key responsibilities

• Architecture definition: Finalize top-level system and micro-architecture specifications alongside technical leadership.
• RTL ownership: Lead VHDL development for critical IP blocks from concept through design freeze.
• Physical design collaboration: Partner with physical design engineers on 12nm floorplanning, synthesis, timing closure (STA), and power optimization.
• Mentorship & oversight: Guide junior block owners through code reviews, micro-architecture design, and block-level verification.
• Design verification: Support testbench architecture and collaborate with verification teams to ensure high coverage.

Required qualifications

• Citizenship requirement: Due to the nature of our defense programs, US citizenship is required.
• ASIC experience: 8+ years of hands-on ASIC design and architecture experience with successful tape-outs.
• Process node: Direct experience with advanced FinFET process nodes (12nm or lower).
• HDL mastery: Deep proficiency in VHDL for synthesizable RTL design.
• EDA toolchains: Hands-on experience with Cadence tools for synthesis, STA, linting, CDC, and power analysis.
• Leadership: Proven track record of mentoring junior and mid-level engineers.