Senior ASIC CAD Engineer: RTL-to-GDSII Automation

Anysilicon; Sunnyvale (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Amazon Lab126 seeks a Senior CAD Engineer to drive ASIC development flows from RTL to GDSII in Sunnyvale, integrating Synopsys, Cadence, and Mentor tools. You will lead automation, CI/CD, and regression efforts while troubleshooting tool issues and collaborating with suppliers to boost design efficiency.

You will also optimize compute/storage for engineering teams, author technical docs, and mentor junior staff in Verilog/SystemVerilog and ASIC methodologies.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years building and supporting CAD infrastructure for ASIC development.
• Experience with version control systems and CI/CD pipeline implementation.
• Ability to write and understand Verilog and SystemVerilog.
• Experience deploying ASIC tools (Verilog simulation, synthesis, place and route, license management).
• Experience leading technical initiatives and key deliverables.

Responsibilities

• Design and maintain ASIC development flows from RTL to GDSII, including RTL generation, simulation, synthesis, place & route, timing analysis, DRC/LVS, and sign-off.
• Deploy and configure EDA tools from vendors across compute infrastructure.
• Develop automation and CI/CD/regression to streamline design tasks and improve consistency.
• Troubleshoot tool issues and collaborate with vendors to resolve bugs and performance bottlenecks.
• Work with IT teams to optimize compute and storage strategies for enhanced engineering efficiency.
• Create and maintain documentation for tool usage, flow methodologies, and best practices.
• Utilize AI tools to accelerate troubleshooting and monitoring of design flows.

Skills

Verilog

SystemVerilog

Python

Bash

CI/CD

Leadership

Scripting

Dashboarding

Education

Bachelor's degree in Electrical Engineering

Tools

Synopsys

Cadence

Mentor/Siemens

Verilog simulation

Place & Route

License management

Job description

Amazon Lab126 seeks a Senior CAD Engineer to drive ASIC development flows from RTL to GDSII in Sunnyvale, integrating Synopsys, Cadence, and Mentor tools. You will lead automation, CI/CD, and regression efforts while troubleshooting tool issues and collaborating with suppliers to boost design efficiency.

You will also optimize compute/storage for engineering teams, author technical docs, and mentor junior staff in Verilog/SystemVerilog and ASIC methodologies.