Senior ASIC CAD Engineer: RTL to GDSII Automation

WarmStart Ltd; Boise, Northern (ID, KY); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Amazon Lab126 is seeking a Senior CAD Engineer to lead ASIC development flows from RTL to GDSII and to deploy multi-vendor EDA tools across compute infrastructure.

You will develop automation, CI/CD pipelines, and tooling to streamline design tasks, while collaborating with IT and vendor teams to optimize performance and reliability. Strong Verilog/SystemVerilog, Python, and CAD infrastructure experience are required.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years building and supporting CAD infrastructure for ASIC development.
• Knowledge of Python and Embedded C programming.
• Ability to write and understand Verilog and SystemVerilog.
• Experience with version control systems and CI/CD pipeline implementation.
• Experience leading technical initiatives and key deliverables.
• Experience supporting deployment of ASIC tools (e.g., Verilog simulation, synthesis, place and route, and license management).

Responsibilities

• Design and maintain ASIC development flows from RTL to GDSII.
• Deploy and configure EDA tools across compute infrastructure.
• Develop automation and CI/CD/regression to streamline design tasks and improve consistency.
• Troubleshoot tool issues and collaborate with vendors to resolve bugs and performance bottlenecks.
• Work with IT teams to optimize compute and storage strategies for enhanced engineering efficiency.
• Create and maintain documentation for tool usage, flow methodologies, and best practices.
• Utilize AI tools to accelerate troubleshooting and monitoring of design flows.

Skills

Verilog

SystemVerilog

Python

Embedded C

RTL coding

EDA tools

CI/CD

Version control

Scripting

ASIC design infrastructure

Education

Bachelor's degree in Electrical Engineering

Tools

Synopsys

Cadence

Mentor/Siemens

Job description

Amazon Lab126 is seeking a Senior CAD Engineer to lead ASIC development flows from RTL to GDSII and to deploy multi-vendor EDA tools across compute infrastructure.

You will develop automation, CI/CD pipelines, and tooling to streamline design tasks, while collaborating with IT and vendor teams to optimize performance and reliability. Strong Verilog/SystemVerilog, Python, and CAD infrastructure experience are required.