Senior Timing Architect for Next‑Gen SoCs & FPGAs

Advanced Micro Devices; San Jose (CA); On-site; USD 210,000 - 260,000; Full time

Job summary

Advanced Micro Devices in San Jose, CA, seeks a senior engineer to define and drive timing, design and power methodologies for advanced nodes, collaborating across architecture, planning, process and design teams to deliver best‑in‑class PPA on monolithic and 2.5D/3DIC adaptive SOCs and FPGAs.

You will translate high‑level requirements into practical methodologies for the design community while focusing on power, performance and area within project schedules and cost constraints.

Qualifications

• Experienced in custom physical design and sign‑off.
• Proficient with industry‑standard PD, analysis, and sign‑off tools.
• Familiar with FPGA implementation workflows and tools.
• Ability to advocate technical solutions in a team setting.
• Excellent written and verbal communication and collaboration.
• Strong scripting skills in Python, Perl or Tcl.

Responsibilities

• Define, develop, optimize and drive design, timing and power methodologies for advanced process nodes.
• Collaborate with implementation and sign‑off teams to ensure robust sign‑off.
• Work with CAD, power integrity, foundry and EDA vendors to assess margins and mitigate risks.

Skills

Physical design

Sign-off

FPGA tools

Cross-functional collaboration

Python/Perl/Tcl

Communication skills

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

Industry‑standard physical design tools

FPGA implementation tools

Job description

Advanced Micro Devices in San Jose, CA, seeks a senior engineer to define and drive timing, design and power methodologies for advanced nodes, collaborating across architecture, planning, process and design teams to deliver best‑in‑class PPA on monolithic and 2.5D/3DIC adaptive SOCs and FPGAs.

You will translate high‑level requirements into practical methodologies for the design community while focusing on power, performance and area within project schedules and cost constraints.