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Apple Inc. is seeking an experienced RFIC Layout Engineer in the San Francisco Bay Area to design and bring up next‑generation wireless CMOS radios.
You will perform detailed transistor‑level layout, collaborate with designers on floorplanning, and ensure layout quality through extraction, DRC/LVS/DFM checks. The role requires strong expertise in RF/analog layout for deep sub‑micron CMOS, device matching, and high-frequency routing, with knowledge of Cadence tools and scripting.
Apple Inc. is seeking an experienced RFIC Layout Engineer in the San Francisco Bay Area to design and bring up next‑generation wireless CMOS radios.
You will perform detailed transistor‑level layout, collaborate with designers on floorplanning, and ensure layout quality through extraction, DRC/LVS/DFM checks. The role requires strong expertise in RF/analog layout for deep sub‑micron CMOS, device matching, and high-frequency routing, with knowledge of Cadence tools and scripting.