Principal Analog/Mixed-Signal ASIC Engineer

Taara; Sunnyvale (CA); Hybrid; USD 258,000 - 294,000; Full time

Job summary

Taara is seeking a Principal Analog/Mixed-Signal ASIC Engineer in Sunnyvale, CA, to work on groundbreaking optical communication systems. You will lead efforts in ASIC design, aiming to deliver high-quality integrated modules and contribute to the team’s drive for innovation.

The ideal candidate has a Ph.D. in Electrical Engineering, over 10 years of relevant experience, and a strong background in ASIC tape-outs and design verification. The position offers a robust salary between $258,000 - $294,000, plus equity and benefits.

Qualifications

• 10+ years of relevant industry experience with achievements in analog/mixed-signal design.
• Deep design expertise in Analog-to-Digital and Digital-to-Analog converters.
• Experience owning top-level ASIC architecture and coordinating teams.

Responsibilities

• Own and deliver custom ASICs for integration with large-scale photonic circuits.
• Contribute to ASIC design and layout, system optimization, and product strategy.
• Demonstrate a strong motivation for technological advancements.

Skills

Analog/Mixed-Signal circuit design

CMOS technologies

ASIC tape-out

Hands-on experience with DRC, LVS, PI, SI

Education

Ph.D. in Electrical Engineering or related field

Tools

Commercial layout verification software

Design Rule Checks (DRC)

Power Integrity (PI)

Signal Integrity (SI)

Job description

About The Team

Born at X, Google's Moonshot Factory, Taara is on a mission to connect billions of people who lack abundant and affordable internet by pioneering high-throughput, long-range free-space optical communication (FSOC). Our links use eye-safe lasers propagating between two terminals to transmit high-speed data wirelessly. Lead the charge in bringing our groundbreaking wireless optical communication to the world. Join us to light the way toward bridging the digital divide and illuminating the future.

About The Role

Taara is seeking a Principal Analog/Mixed-Signal ASIC Engineer to work on the next generation of co-integrated electronic and photonic modules. You will be part of an R&D team developing cutting‑edge wireless optical communication systems based on integrated optical phased arrays.

The successful candidate will lead ASIC tape‑out efforts, own the ASIC top‑level architecture, and drive the delivery and validation of ASIC dies. This includes making hands‑on contributions to Analog/Mixed‑Signal (AMS) ASIC designs and coordinating a small team of ASIC design and layout engineers. The role requires extensive experience in ASIC design and layout—including top‑level ownership of ASIC tape‑outs at leading commercial foundries—and deep expertise in either or both of these two categories: high‑precision AMS circuits and high‑speed wireline/silicon photonics interface circuits.

We are looking for a highly motivated individual who thrives in ambiguity, enjoys working in a small, dynamic team environment, and has a passion for solving challenging problems that lead to high‑impact technological advances.

How You Will Make a 10x Impact

• Own and deliver custom ASICs for co‑integration with large‑scale photonic integrated circuits to form record‑breaking integrated modules.
• Contribute to ASIC design and layout, system‑level optimization, and product strategy.
• Demonstrate a strong motivation to make the world a better place through technology and a desire to be part of the team making this happen.

What You Should Have

• Ph.D. in Electrical Engineering or a related field.
• 10 or more years of relevant industry experience with demonstrated achievements in analog/mixed‑signal circuit design and implementation in modern CMOS technologies.
• Demonstrated deep design expertise in one or both of these categories:
  • High‑precision designs: Analog‑to‑digital and digital‑to‑analog converters, bandgap references, voltage regulators, amplifiers, and other supporting circuitry. Integration and co‑simulation of analog and digital circuits in the context of mixed‑signal design and verification.
  • High‑speed designs: Front‑end circuits for optical communication, including modulator drivers and transimpedance amplifiers (TIAs) operating at tens of GHz, and broadband circuits for serial links including receivers, transmitters, and equalizers. Electromagnetic design of high‑frequency transmission lines, inductors, and other passive elements.
• Experience owning top‑level ASIC architecture and coordinating engineering teams.
• Hands‑on experience leading multiple ASIC tape‑outs at commercial foundries.
• Hands‑on experience with Design Rule Checks (DRC), Layout Versus Schematic (LVS), Power Integrity (PI), and Signal Integrity (SI) verification.

It Would Be Great If You Also Had

• Experience with planning and executing verification of large Systems‑on‑Chip (SoCs) incorporating complex digital logic and large numbers of custom‑designed blocks.
• Experience with hardware description languages, such as Register‑Transfer Level (RTL) code, and RTL‑to‑GDS design flows using industry‑standard EDA tools for synthesis, timing analysis, and place‑and‑route.
• Experience with versioning tools such as SOS and Git.
• Experience with commercial layout verification software (Calibre or equivalent).
• Excellent communication and presentation skills, with the ability to work effectively with senior external partners.
• Hands‑on experience advancing a product from the prototype phase to the final production stage.

Location & Compensation

A hybrid or onsite setup in Sunnyvale, CA, is preferred, though remote work can be considered. Relocation assistance can be provided.

The US salary range for this full‑time position is $258,000 - $294,000 (inclusive of bonus at target) + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your location during the hiring process.