Senior Analog Layout Engineer – Optics & Tapeout Lead

Cisco Systems; Carlsbad (CA); Presencial; USD 149.000 - 218.000; Jornada completa

Descripción de la vacante

Cisco Systems seeks a Senior Analog/Layout Engineer to architect physical blueprints for high-speed optical interconnects on the Silicon One platform. You will own block-to-top integration for 100G–400G lambda architectures, guiding from floorplanning through post-layout signoff and silicon bring-up.

You will collaborate with CAD, circuit, and packaging teams to optimize parasitics, thermal behavior, and signal integrity while mentoring junior engineers and shaping layout methodologies in a

Formación

• Bachelor's degree plus 7 years of related experience, or Master's with 4 years, or PhD with 1 year
• Experience supporting block-level layout through tapeout
• Experience in physical verification and custom layout design for FINFET 7nm/5nm/3nm
• Experience with Cadence Virtuoso or similar custom layout tools
• Experience with ASIC/SoC tapeout processes and scripting (Python, Perl, TCL) for layout automation

Responsabilidades

• Power Next-Gen Optics: build and optimize analog/mixed-signal layouts for 100G–400G/lambda optical solutions
• Own the Silicon Lifecycle: drive full-flow from concept to sign-off, tapeout and bring-up
• Solve High-Speed Challenges: manage parasitics, SI and thermal tradeoffs with CAD teams
• Set the Standard: shape design methodologies and mentor rising engineers

Conocimientos

Analog layout

Physical verification

Tapeout experience

Scripting (Python/Perl/TCL)

Educación

Bachelor's degree in related field

Master's degree (advantage)

PhD (advantage)

Herramientas

Cadence Virtuoso

Calibre

Descripción del empleo

Cisco Systems seeks a Senior Analog/Layout Engineer to architect physical blueprints for high-speed optical interconnects on the Silicon One platform. You will own block-to-top integration for 100G–400G lambda architectures, guiding from floorplanning through post-layout signoff and silicon bring-up.

You will collaborate with CAD, circuit, and packaging teams to optimize parasitics, thermal behavior, and signal integrity while mentoring junior engineers and shaping layout methodologies in a