Lead High-Speed Analog Layout Architect

Celero Communications, Inc.; San Jose, Northern (CA, KY); Hybrid; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal High-Speed Analog Layout Design Engineer in San Jose, CA to drive layout of analog/mixed-signal IP blocks for state-of-the-art optical communication systems.

You will lead floor planning, collaborate with schematic designers, mentor junior engineers, and ensure first-pass silicon success through rigorous LVS/DRC/PERC checks and advanced layout techniques.

Qualifications

• 10+ years hands-on analog/mixed-signal layout experience in advanced CMOS/FinFET
• Proven track record leading IP layout macros or full-chip layout
• Experience with TSMC FinFET nodes (N3/N5/N7/N16)
• Strong understanding of LOD, WPE, OSE, LDE and layout effects on performance
• Proficiency in floor planning, hierarchical block integration, routing and power/ground grid design
• Experience with LVS, DRC, PERC, Density, DFM, ERC and Antenna rules
• Collaborative experience with international/remote teams
• Ability to present trade-offs and status clearly to cross-functional teams
• Experience with revision control systems for layout design management

Responsibilities

• Lead the physical layout design of analog/mixed-signal macros from floor planning to verification
• Collaborate with schematic designers to optimize layouts for performance and matching
• Mentor junior layout engineers across time zones
• Perform and debug LVS, DRC, PERC, ERC checks using industry tools
• Contribute to chip-level planning including top-level floor planning and power routing
• Participate in layout design reviews and ensure schedule adherence
• Support automation through scripting (SKILL, TCL, Python)

Skills

Analog/mixed-signal layout

Floor planning

Routing and power/ground design

LVS/DRC/PERC/ERC checks

Cadence Virtuoso

Calibre

TP/IP integration

Schematic/layout collaboration

Tools

Pegasus

Calibre

Cadence Virtuoso

Job description

Celero Communications, Inc. is seeking a Principal High-Speed Analog Layout Design Engineer in San Jose, CA to drive layout of analog/mixed-signal IP blocks for state-of-the-art optical communication systems.

You will lead floor planning, collaborate with schematic designers, mentor junior engineers, and ensure first-pass silicon success through rigorous LVS/DRC/PERC checks and advanced layout techniques.