Senior Analog Layout Lead for Photonic AI Silicon

LUMILENS; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health insurance

Professional development

Certification support

Access to cutting-edge technology

Job summary

Lumilens is seeking an experienced Analog Layout Lead to drive full-custom analog/mixed-signal layout for next-generation silicon platforms in the San Jose area. You will lead complex physical implementation, partner with circuit and physical design teams, and establish layout methodologies that ensure performance, manufacturability, and tape-out readiness across multiple programs.

You will own parasitic-aware layout strategies, collaborate on LVS/DRC, and provide technical guidance while

Qualifications

• 8+ years of full-custom analog/mixed-signal layout for production silicon in advanced CMOS nodes (28nm or below).
• Experience leading layout of PLLs, LDOs, data converters, and high-speed interfaces.
• Experience defining layout methodologies for matching, shielding, noise isolation, and signal integrity.
• Experience collaborating with circuit design teams to translate simulations into layout constraints and verification.

Responsibilities

• Lead full-custom analog/mixed-signal layout across complex blocks.
• Define analog layout methodologies and design rules for the team.
• Drive parasitic-aware layouts to meet noise and SI requirements.
• Translate schematic intent into optimized physical implementations and verify LVS/DRC.
• Own sign-off readiness across multiple silicon programs and nodes.
• Provide layout direction and review layouts for consistency and quality.
• Collaborate with process/PD kits teams for new node bring-up and PDK qualification.
• Shape long-term physical design roadmaps and methodologies.

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Cadence Virtuoso

Spectre

Calibre

Parasitic extraction

Job description

Lumilens is seeking an experienced Analog Layout Lead to drive full-custom analog/mixed-signal layout for next-generation silicon platforms in the San Jose area. You will lead complex physical implementation, partner with circuit and physical design teams, and establish layout methodologies that ensure performance, manufacturability, and tape-out readiness across multiple programs.

You will own parasitic-aware layout strategies, collaborate on LVS/DRC, and provide technical guidance while