Senior Analog Layout Engineer for High-Speed Mixed-Signal ICs

Arrow Electronics

United States

Remote

USD 120,000 - 180,000

Full time

9 days ago

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Job summary

Arrow Electronics' eInfochips unit seeks an Analog Layout Engineer in Austin, TX to design physical silicon for high-speed mixed-signal circuits (SerDes, ADCs, DACs, PLLs). You will own block- and chip-top-level floor planning, layout, and integration.

The ideal candidate has 5–12+ years of hands-on IC layout in deep sub-micron CMOS/FinFET nodes (TSMC N3/N5/N7) and proven ability to meet DRC/LVS/ERC, with ESD and layout-dependent effects experience.

Qualifications

Reliability & verification: ensure closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection.
5–12+ years of hands-on custom IC layout experience in deep sub-micron CMOS/FinFET nodes (TSMC N3, N5, N7).
Experience at lower nodes (N3, N5) is critical for this position.
Education: Bachelor's degree.

Responsibilities

Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design.
Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields).
Reliability & Verification: Ensure complete closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection.