Senior AI Hardware Co-Design Engineer (TPU) - Equity

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking a Senior Performance Co-Design Engineer for Google Cloud TPU in Sunnyvale, CA. You’ll shape AI/ML hardware acceleration, drive co-design across software and hardware teams, and help push TPU architecture to the next level for demanding models.

You’ll conduct performance studies, build simulation and profiling tools, and partner with researchers to improve LLM inference latency and throughput while aligning with roadmap goals for Cloud Silicon.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 8 years of experience in performance modeling/engineering, computer architecture, codesign, or systems engineering.
• Experience programming in C++ or Python.

Responsibilities

• Conduct comprehensive serving performance studies on current and emerging first‑party and third‑party LLMs.
• Develop and maintain advanced simulation, profiling, and modeling tools to identify bottlenecks, understand key characteristics, and project serving workload performance.
• Partner with model researchers, software teams, and hardware teams to co‑design architectural improvements tailored to LLM inference latency and throughput.
• Drive data‑backed decisions that influence the roadmap for future TPU and Cloud Silicon architectures.

Skills

8 years of experience in performance

C++/Python experience

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

C++

Python

Job description

Google is seeking a Senior Performance Co-Design Engineer for Google Cloud TPU in Sunnyvale, CA. You’ll shape AI/ML hardware acceleration, drive co-design across software and hardware teams, and help push TPU architecture to the next level for demanding models.

You’ll conduct performance studies, build simulation and profiling tools, and partner with researchers to improve LLM inference latency and throughput while aligning with roadmap goals for Cloud Silicon.