Senior AI-Driven Semiconductor Packaging Design Engineer

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 120,000 - 190,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Robust paid time-off program

Paid holidays

Paid family leave

Benefits guide online

Job summary

Micron Technology in Boise, Idaho, seeks a highly experienced Design Engineer to advance Advanced Packaging Technology Development. You will drive electrical, thermal, and thermo-mechanical design for next‑generation memory packages (HBM, W2W, COW, Flip Chip, TSV) and collaborate across global teams.

A strong background in AI/ML‑enabled design workflows is essential, with 15–20 years in engineering and an MS/PhD.

Qualifications

• MS or PhD in Electrical Engineering, Materials Science, Applied Physics, or related field.
• 15–20 years in an engineering role with 10+ years in package analysis and validation.
• Strong understanding of thermal impedance and design impacts.

Responsibilities

• Maintain deep knowledge of HBM, W2W, COW, Flip Chip, and TSV packaging.
• Drive design advancements through parasitics, insertion loss, and impedance analysis.
• Propose thermal improvements and initiate related projects.
• Apply Chip-Package Interactions in 2.5D/3D systems and validate models.
• Collaborate with vendors and labs to test dielectric constants and decay values.
• Integrate AI workflows into package design and technology evaluations.
• Advance AI-enabled tech development for packaging and heterogeneous integration.

Skills

Advanced Packaging Knowledge

AI/ML integration into workflows

DOE/statistical analysis (JMP or-equv)

Electrical/Thermal/Mechanical package/

Education

MS or PhD in Electrical Engineering, Materials Science, Applied Physics, or related field

Tools

Cadence layout tools

MATLAB

JMP

Excel

Job description

Micron Technology in Boise, Idaho, seeks a highly experienced Design Engineer to advance Advanced Packaging Technology Development. You will drive electrical, thermal, and thermo-mechanical design for next‑generation memory packages (HBM, W2W, COW, Flip Chip, TSV) and collaborate across global teams.

A strong background in AI/ML‑enabled design workflows is essential, with 15–20 years in engineering and an MS/PhD.