Senior DRAM Memory Design Engineer | AI-Driven Innovation

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 170,000 - 210,000; Full time

Benefits offered by this job

Medical, Dental, Vision

Paid time off

Relocation assistance

Job summary

Micron Technology, Inc. in Boise, ID is seeking a Semiconductor Design Engineer (Principal / MTSS / SMT) to design and optimize next-generation DRAM products.

You will collaborate with global teams to balance performance, power, reliability, and cost, while mentoring engineers. Responsibilities include leading circuit development, floor-planning, and silicon validation, with opportunities to influence technical direction and AI-assisted design flows.

Qualifications

• Bachelor's in Electrical Engineering or related field with senior-level semiconductor design experience.
• 10+ years with MSEE or 12+ years with BSEE in DRAM/semiconductor design and leadership.
• Proficient in Verilog modeling, PDN analysis, and circuit verification methodologies.

Responsibilities

• Design and optimize digital and analog circuits for next-gen DRAM products.
• Lead circuit development, simulation, verification, and silicon validation.
• Drive floor-planning, layout optimization, and tape-out activities.
• Advance AI-assisted design through collaboration with partners.
• Provide technical leadership and mentorship to engineers.

Skills

CMOS design

Device physics

State machine logic

Design verification

Verilog modeling

PDN analysis

Python scripting

Tcl scripting

Perl scripting

Analytical thinking

Communication

Collaboration

Education

Bachelor's degree in Electrical Engineering or related field

MSEE

BSEE with 12+ years experience

SMTS level with 15+ years experience

Tools

Verilog tools

Schematic tools

HSPICE

FINESIM

Job description

Micron Technology, Inc. in Boise, ID is seeking a Semiconductor Design Engineer (Principal / MTSS / SMT) to design and optimize next-generation DRAM products.

You will collaborate with global teams to balance performance, power, reliability, and cost, while mentoring engineers. Responsibilities include leading circuit development, floor-planning, and silicon validation, with opportunities to influence technical direction and AI-assisted design flows.