Senior AI Accelerator Architect for Energy-Efficient ASICs

Normal Computing Corporation; Palo Alto (CA); On-site; USD 250,000 - 420,000; Full time

Job summary

Normal Computing is seeking an experienced Hardware ASIC Architect to define the silicon and microarchitecture for a novel AI accelerator intended for LLM and diffusion model inference. You will drive architectural trade-offs to achieve large energy-efficiency gains and lead co-design with compiler, RTL, and analog teams.

You will translate workloads into hardware specifications, build performance models, and guide prototyping strategies with FPGA partners to de-risk tapeout.

Qualifications

• Degree in Electrical Engineering or related field; PhD welcome but not required.
• Experience in architecture or microarchitecture of high‑performance digital systems.
• Ability to translate workloads into datapath widths and power estimates.
• Experience with simulation-driven architecture and RTL collaboration.
• Familiarity with quantization and reduced-precision approaches.

Responsibilities

• Define silicon architecture and microarchitecture for AI accelerator compute blocks.
• Translate workload analysis into hardware specifications for RTL teams.
• Defend full-stack PPA tradeoffs across algorithm, memory, interconnect, and design constraints.
• Co-design ISA with compiler and align microarchitecture with software model.
• Direct pre-silicon prototyping and de-risk decisions with FPGA and System teams.
• Stay current with AI accelerator research and articulate differences from rivals.

Skills

Compute Architecture

Workload-to-Hardware Translation

Full-Stack PPA Tradeoffs

ISA Co-Design

Prototyping Strategy

Research Fluency

Python

C++

SystemVerilog

Education

Electrical Engineering degree

Tools

SystemVerilog

Python

C++

Job description

Normal Computing is seeking an experienced Hardware ASIC Architect to define the silicon and microarchitecture for a novel AI accelerator intended for LLM and diffusion model inference. You will drive architectural trade-offs to achieve large energy-efficiency gains and lead co-design with compiler, RTL, and analog teams.

You will translate workloads into hardware specifications, build performance models, and guide prototyping strategies with FPGA partners to de-risk tapeout.