Senior AI/ML ASIC Performance Architect

Sandisk; Milpitas (CA); On-site; USD 180,000 - 250,000; Full time

Benefits offered by this job

Medical/dental/vision insurance

Stock purchase plan

Tuition reimbursement

401(k) plan

Job summary

Sandisk seeks an AI/ML ASIC Performance Engineer to develop AI Storage Solutions based architectures and accelerator frontends. You will drive frontend architecture, collaborate with RTL/DV/ FW teams, and assess performance, power, area, and endurance of the product.

You will work with design and product planning teams to define architectural requirements meeting PPA targets, and guide pre-silicon verification and post-silicon validation throughout execution.

Qualifications

• Bachelor's or Master's in Computer/Electrical Engineering with 1–3 years of hands-on architecture experience authoring specifications.
• Strong background architecting ASIC/SoC or I/O subsystems involving PCIe/UCIe/CXL and DMA engines.
• Knowledge of I/O Subsystems interacting with embedded subsystems (x86, RISCV, ARM) and host CPUs.
• Good understanding of computer/graphics architecture, ML/LLM.
• Experience architecting GPU/TPU/xPU Accelerator systems with high bandwidth memory hierarchies and frontend architectures for large LLM training/inference.

Responsibilities

• Drive AI/ML ASIC architecture integrating AI Storage with accelerators and I/O subsystems.
• Author architecture specifications for AI/ML xPU Accelerators.
• Define SoC DMA and I/O subsystem architectures and their interactions with processors and memory.
• Guide pre/post-silicon design/verification and post-silicon validation.
• Collaborate with customers and cross-functional teams to scope SoC requirements and tradeoffs.

Skills

ASIC/SoC architecture

I/O subsystems PCIe/UCIe/CXL

DMA engines

ML/LLM aware architectures

ARM/RISC-V/embedded subsystems

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

UCIe protocol

PCIe

CXL

NVLink familiarity

Job description

Sandisk seeks an AI/ML ASIC Performance Engineer to develop AI Storage Solutions based architectures and accelerator frontends. You will drive frontend architecture, collaborate with RTL/DV/ FW teams, and assess performance, power, area, and endurance of the product.

You will work with design and product planning teams to define architectural requirements meeting PPA targets, and guide pre-silicon verification and post-silicon validation throughout execution.