Silicon Architect, Diffusion ASICs

Anysilicon; New York, Northern (NY, KY); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Normal Computing Corporation in New York, NY is seeking a talented engineer to contribute to the architecture and microarchitecture of AI accelerator compute blocks, ensuring research translates into silicon solutions. You will define PE array designs, translate workload analysis into hardware specs for RTL engineers, and evaluate PPA tradeoffs across the stack.

Collaborate with the compiler lead on ISA co-design to ensure the compute tile is programmable.

Qualifications

• Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent; PhD preferred but not required.
• Experience in architecture/microarchitecture of high-performance digital systems, AI accelerators, or complex logic.
• Ability to translate workload analysis into hardware specifications for RTL.
• Experience with simulation-driven architecture and cycle-accurate models.

Responsibilities

• Define architecture and microarchitecture of AI accelerator compute blocks, focusing on PE array design.
• Translate workload analysis into hardware specifications for RTL engineers.
• Evaluate PPA tradeoffs across the architecture stack with partial data.
• Collaborate with the compiler lead on ISA co-design for a programmable compute tile.
• Oversee FPGA prototyping to validate architecture decisions and bring-up.
• Stay updated on AI accelerator research and articulate Normal Computing's approach.

Skills

Performance modeling

SystemVerilog

RTL design

Hardware co-design

Education

Bachelors in EE/CS

PhD preferred

Tools

Python

C++

Job description

Normal Computing Corporation, New York, NY

Job Description:

Normal Computing is at the forefront of developing innovative software and hardware solutions for the semiconductor industry and AI infrastructure. With teams across major global cities, we are focused on creating ASICs specifically designed for image and video diffusion inference, challenging the conventional GPU paradigm. We seek a talented individual to contribute to the architecture and microarchitecture of our AI accelerator compute blocks, ensuring our research translates into tangible silicon solutions.

Responsibilities:

• Define the architecture and microarchitecture of novel AI accelerator compute blocks, focusing on PE array design and efficiency techniques.
• Translate workload analysis and research findings into clear hardware specifications for implementation by RTL engineers.
• Evaluate PPA tradeoffs across the architecture stack, making informed decisions based on incomplete data.
• Collaborate with the compiler lead on ISA co-design to ensure the compute tile is both compilable and programmable.
• Oversee FPGA prototyping to validate architecture decisions and drive implementation through to bring-up.
• Stay updated on AI accelerator research and articulate Normal's unique approach in comparison to existing solutions.

Qualifications:

• Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience; PhD preferred but not required.
• Substantial experience in architecture or microarchitecture of high-performance digital systems, particularly AI accelerators or complex logic.
• Fluency in translating algorithm-level analysis into hardware specifications and vice versa.
• Experience with simulation-driven architecture and cycle-accurate models for design decisions.
• Familiarity with quantization and reduced-precision approaches for inference and their hardware implications.
• Experience writing microarchitecture specifications and collaborating with RTL engineers during implementation.

Skills:

• Proficiency in Python or C++ for performance modeling and analysis.
• Familiarity with SystemVerilog or equivalent RTL.
• Strong analytical skills to navigate between algorithm-level behavior and hardware design.
• Ability to work in a dynamic environment where architecture is actively being developed.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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