AI Accelerator Architect — Ultra-Efficient LLM Inference HW

Normal Computing Corp.; Palo Alto (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Normal Computing seeks a Hardware ASIC Architect to define the silicon and system microarchitecture for our unconventional compute platform. You will drive architectural trade-offs to enable a large leap in energy efficiency for LLM and diffusion model inference, translating transformer and diffusion flows into custom compute tiles and interconnects.

You will work with compiler, RTL, and analog teams to build performance models, write microarchitecture specs, and ensure maximum

Qualifications

• A degree in Electrical Engineering, Computer Engineering, or Computer Science; PhD welcome but not required.
• Extensive experience in architecture or microarchitecture of high‑performance digital systems: AI accelerators or similar.
• Ability to translate workload profiles into datapath widths and power estimates without losing thread on either side.
• Experience with simulation-driven architecture and design decisions before RTL exists.

Responsibilities

• Define silicon and system microarchitecture for a custom AI accelerator.
• Translate workload analyses into hardware specifications and microarchitecture docs.
• Defend full-stack PPA tradeoffs across algorithm, memory, interconnect, and physical design.
• Partner with compiler teams on ISA co-design and with RTL engineers through implementation.
• Direct pre-silicon validation strategies and de-risk decisions before tapeout.
• Stay fluent in AI accelerator research and articulate unique advantages.

Skills

AI accelerator

Microarchitecture

RTL design

Python/C++

SystemVerilog

Performance modeling

Quantization

Pre-silicon validation

Workload translation

Education

B.S. or higher in Electrical/Computer Engineering

PhD welcomed but not required

Tools

RTL simulation tools

Cycle-accurate simulators

Job description

Normal Computing seeks a Hardware ASIC Architect to define the silicon and system microarchitecture for our unconventional compute platform. You will drive architectural trade-offs to enable a large leap in energy efficiency for LLM and diffusion model inference, translating transformer and diffusion flows into custom compute tiles and interconnects.

You will work with compiler, RTL, and analog teams to build performance models, write microarchitecture specs, and ensure maximum