AI Accelerator Architect for Diffusion Inference ASICs

Anysilicon; New York, Northern (NY, KY); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Normal Computing Corporation in New York, NY is seeking a talented engineer to contribute to the architecture and microarchitecture of AI accelerator compute blocks, ensuring research translates into silicon solutions. You will define PE array designs, translate workload analysis into hardware specs for RTL engineers, and evaluate PPA tradeoffs across the stack.

Collaborate with the compiler lead on ISA co-design to ensure the compute tile is programmable.

Qualifications

• Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent; PhD preferred but not required.
• Experience in architecture/microarchitecture of high-performance digital systems, AI accelerators, or complex logic.
• Ability to translate workload analysis into hardware specifications for RTL.
• Experience with simulation-driven architecture and cycle-accurate models.

Responsibilities

• Define architecture and microarchitecture of AI accelerator compute blocks, focusing on PE array design.
• Translate workload analysis into hardware specifications for RTL engineers.
• Evaluate PPA tradeoffs across the architecture stack with partial data.
• Collaborate with the compiler lead on ISA co-design for a programmable compute tile.
• Oversee FPGA prototyping to validate architecture decisions and bring-up.
• Stay updated on AI accelerator research and articulate Normal Computing's approach.

Skills

Performance modeling

SystemVerilog

RTL design

Hardware co-design

Education

Bachelors in EE/CS

PhD preferred

Tools

Python

C++

Job description

Normal Computing Corporation in New York, NY is seeking a talented engineer to contribute to the architecture and microarchitecture of AI accelerator compute blocks, ensuring research translates into silicon solutions. You will define PE array designs, translate workload analysis into hardware specs for RTL engineers, and evaluate PPA tradeoffs across the stack.

Collaborate with the compiler lead on ISA co-design to ensure the compute tile is programmable.