Semiconductor Debug Engineer — High-Speed Validation

UST; San Jose (CA); On-site; USD 75,000 - 113,000; Full time

Benefits offered by this job

401(k) matching

Medical, dental, and vision insurance

Paid vacation and holidays

Paid sick leave

Possible HSA/FSAs

Job summary

UST is seeking a Debug Engineer for Semiconductor Product Validation in San Jose, CA. You will debug and troubleshoot test benches and hardware setups, execute tests, collect data, and summarize results.

The role requires hands-on use of Network Analyzers, BERT, and high-speed oscilloscopes with Python scripting for data collection. Location is San Jose, CA, with compensation ranging from $75,000 to $113,000 annually.

Qualifications

• 4+ years of hands-on experience in hardware validation and testing.
• Experience with Network Analyzer, BERT, and high‑speed oscilloscopes.
• Good understanding of S-parameters and high‑speed channel measurements.
• Basic knowledge of SERDES and Python scripting.
• Experience in hardware validation, debugging, and lab testing.

Responsibilities

• Execute tests, collect data, and summarize results.
• Perform high-speed channel calibration using a Network Analyzer.
• Measure transmitter/channel parameters using high-speed oscilloscopes.
• Support test automation and data collection using Python scripts.

Skills

Python scripting

Hardware testing

4+ years experience

Tools

Network Analyzer

BERT

Oscilloscope

Job description

UST is seeking a Debug Engineer for Semiconductor Product Validation in San Jose, CA. You will debug and troubleshoot test benches and hardware setups, execute tests, collect data, and summarize results.

The role requires hands-on use of Network Analyzers, BERT, and high-speed oscilloscopes with Python scripting for data collection. Location is San Jose, CA, with compensation ranging from $75,000 to $113,000 annually.