Senior High-Speed Silicon Validation Engineer

Qualcomm; San Diego (CA); On-site; USD 118,000 - 177,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a Hardware Engineering specialist for the Post Silicon Engineering group to develop test solutions for highly integrated SOCs and to define/test methodologies for high speed SERDES interfaces (PCIe, USB4, UFS, DP, MIPI).

You will drive characterization plans, support first silicon bring up, analyze parametric performance across conditions, and collaborate with IC Design and Systems Engineering to resolve issues while maintaining rigorous documentation and

Qualifications

• 5+ years in High Speed Silicon Validation.
• Bachelor’s degree with 2+ years hardware engineering experience or equivalent.
• Master’s or PhD with 1+ year hardware experience preferred, strong analytical skills.

Responsibilities

• Define and execute test methodologies for High Speed SERDES interfaces (PCIe, USB4, UFS, DP, MIPI).
• Develop characterization plans to optimize design parameters and validate electrical compliance.
• Lead first silicon bring-up and debug with cross‑functional teams to qualify designs.
• Analyze parametric performance across operating conditions and configurations.

Skills

High speed validation

Python

C#

Oscilloscopes

TDRs/VNAs

J-BERT

Education

Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

Master’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

Tools

Si test equipment

Job description

Qualcomm Technologies, Inc. is seeking a Hardware Engineering specialist for the Post Silicon Engineering group to develop test solutions for highly integrated SOCs and to define/test methodologies for high speed SERDES interfaces (PCIe, USB4, UFS, DP, MIPI).

You will drive characterization plans, support first silicon bring up, analyze parametric performance across conditions, and collaborate with IC Design and Systems Engineering to resolve issues while maintaining rigorous documentation and