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Cadence is seeking a Post-Silicon Validation Engineering Intern in San Jose, CA to validate system-level and electrical performance of internal silicon test chips. You will debug issues in close collaboration with analog and digital design teams and deliver characterization reports.
The role emphasizes cross-functional work to ensure product functionality and reliability. The ideal candidate is pursuing an EE degree with 0-2 years of experience, strong communication skills, and the ability to
Cadence is seeking a Post-Silicon Validation Engineering Intern in San Jose, CA to validate system-level and electrical performance of internal silicon test chips. You will debug issues in close collaboration with analog and digital design teams and deliver characterization reports.
The role emphasizes cross-functional work to ensure product functionality and reliability. The ideal candidate is pursuing an EE degree with 0-2 years of experience, strong communication skills, and the ability to