Lead Post-Silicon Validation Engineer for High-Speed I/O

Astera Labs; San Jose (CA); On-site; USD 185,000 - 240,000; Full time

Job summary

Astera Labs seeks a Principal Validation Engineer in San Jose to lead post-silicon validation of high-speed interfaces like PCIe and Ethernet. You will automate IC and board tests, design experiments to root-cause issues, and report conformance while partnering with customers to quantify margins.

The role requires 10+ years in SoC validation, strong scripting (Python), and lab skills with BERT, VNA, and oscilloscopes.

Qualifications

• Bachelor’s in Electrical or Computer Engineering; Master’s preferred.
• 10+ years’ experience testing or validating SoC/silicon with high-speed IO interfaces.
• Ability to prioritize tasks, plan for internal meetings, and work with minimal supervision.
• Entrepreneurial, customer-focused mindset and proactive problem solving.

Responsibilities

• Develop and execute electrical validation tests for parametric device performance and margins.
• Automate testing of ICs and board products; design experiments to root-cause issues.
• Report results and conformance; quantify margins with internal customers.
• Collaborate with internal teams to ensure robustness of products for AI/ML applications.

Skills

Python scripting

Problem solving

Customer focus

Leadership / tech lead

Test automation

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree preferred

Tools

Git

Cadence

Altium

Oscilloscope

BERT

VNA

Job description

Astera Labs seeks a Principal Validation Engineer in San Jose to lead post-silicon validation of high-speed interfaces like PCIe and Ethernet. You will automate IC and board tests, design experiments to root-cause issues, and report conformance while partnering with customers to quantify margins.

The role requires 10+ years in SoC validation, strong scripting (Python), and lab skills with BERT, VNA, and oscilloscopes.