Secure ASIC Design & Integration Engineer

Apple Inc.; Cupertino, Northern (CA, KY); Hybrid; USD 150,000 - 278,000; Full time

Benefits offered by this job

Stock programs

RSU awards

Stock Purchase Plan

Medical benefits

Education reimbursement

Relocation assistance

Job summary

Apple Inc. in Cupertino, California is seeking an ASIC Design and Integration Engineer for Silicon Security. You will architect and implement secure subsystems, protecting data across Apple SoCs, and work with cryptographic engines and side-channel defenses.

You will design micro-architecture, RTL and integrate security IPs, collaborating across teams to meet timing, performance and security goals.

Qualifications

• BS in Electrical Engineering, Computer Engineering or a related field.
• 3 years of industry RTL design experience with Verilog or SystemVerilog.

Responsibilities

• Architect and design security features for high performance, area, and power efficiency in RTL blocks.
• Integrate security IPs into subsystems ensuring timing and security requirements.
• Resolve integration issues across IP blocks and coordinate interfaces.
• Drive front-end quality from RTL to netlist including Lint, CDC/RDC, UPF, timing and synthesis.
• Leverage AI-assisted tools to enhance design quality and productivity.

Skills

RTL design (Verilog SystemVerilog)

Digital design fundamentals

AMBA AXI/AHB/APB

Cryptography basics

Education

BS in Electrical/Computer Engineering or related field

Job description

Apple Inc. in Cupertino, California is seeking an ASIC Design and Integration Engineer for Silicon Security. You will architect and implement secure subsystems, protecting data across Apple SoCs, and work with cryptographic engines and side-channel defenses.

You will design micro-architecture, RTL and integrate security IPs, collaborating across teams to meet timing, performance and security goals.