Secure ASIC Design & Integration Engineer

Socket.dev; Cupertino (CA); On-site; USD 190,000 - 240,000; Full time

Job summary

Apple's Silicon Security team is seeking an ASIC Design Engineer to build secure subsystems for the Apple SoC, defending against side-channel attacks and protecting data across devices.

Responsibilities include architecting security features, integrating IPs, and driving RTL-to-netlist quality with timing and power efficiency. Familiarity with cryptography and AMBA protocols is beneficial.

Qualifications

• BS in Electrical Engineering, Computer Engineering or a relevant field with 0 years of experience.
• Experience with RTL design, Verilog or SystemVerilog is preferred.

Responsibilities

• Architect and design security features for secure subsystems.
• Integrate security IPs and ensure timing, performance, and security.
• Resolve integration issues across IP blocks and coordinate with IP owners.
• Drive front-end quality flows from RTL to netlist, including lint, CDC/RDC analysis, UPF, timing, and synthesis.
• Leverage AI-assisted tools to enhance design quality.

Skills

RTL design

Verilog

SystemVerilog

CDC analysis

RDC analysis

UPF

timing closure

cryptography

AMBA protocols

hardware security

Education

BS in Electrical Engineering or related field

Job description

Apple's Silicon Security team is seeking an ASIC Design Engineer to build secure subsystems for the Apple SoC, defending against side-channel attacks and protecting data across devices.

Responsibilities include architecting security features, integrating IPs, and driving RTL-to-netlist quality with timing and power efficiency. Familiarity with cryptography and AMBA protocols is beneficial.