Silicon Security ASIC Engineer — Secure SoC Innovation

Apple Inc.; Cupertino (CA); On-site; USD 129,000 - 195,000; Full time

Benefits offered by this job

Medical and dental coverage

Retirement benefits

Employee stock programs

Tuition reimbursement

Job summary

Apple Inc. is seeking an ASIC Design and Integration Engineer for Silicon Security in Cupertino. You will design secure RTL blocks and integrate security IPs across the SoC, focusing on protecting data and preventing side-channel attacks.

Responsibilities include end-to-end RTL-to-netlist flows, timing and power-aware design, and collaboration with architecture and verification teams to deliver high‑performance, secure subsystems.

Qualifications

• BS in Electrical/Computer Engineering required.
• Experience with RTL design using Verilog or SystemVerilog preferred.
• Familiarity with security concepts and cryptography is useful.

Responsibilities

• Architect and design secure RTL blocks with performance, area, and power in mind.
• Integrate security IPs into secure subsystems meeting timing and security goals.
• Resolve integration issues across IP blocks and coordinate interfaces.
• Drive front-end quality flows from RTL to netlist including Lint, CDC/RDC, UPF, timing and synthesis.
• Leverage AI-assisted tools to enhance design quality and productivity.

Skills

RTL design

Verilog

SystemVerilog

CDC analysis

RDC analysis

UPF

Synthesis & timing

Cryptography

Hardware security concepts

AMBA protocols

Clock and reset architecture

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Job description

Apple Inc. is seeking an ASIC Design and Integration Engineer for Silicon Security in Cupertino. You will design secure RTL blocks and integrate security IPs across the SoC, focusing on protecting data and preventing side-channel attacks.

Responsibilities include end-to-end RTL-to-netlist flows, timing and power-aware design, and collaboration with architecture and verification teams to deliver high‑performance, secure subsystems.