ASIC Design and Integration Engineer

Apple Inc.; Cupertino (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Apple Inc.’s Silicon Engineering team seeks an experienced ASIC Design Engineer to develop custom SoCs that power our products. You will design, implement, and verify complex RTL using SystemVerilog, and collaborate with cross‑functional teams to deliver high‑performance solutions.

The role focuses on front‑end design, synthesis, timing and power analysis, integration, and thorough documentation to meet stringent PPA goals across cutting‑edge projects.

Qualifications

• BS + 10 years of relevant industry experience.
• Proficiency in SystemVerilog and RTL design.
• Experience with ASIC design, RTL verification, and synthesis.
• Strong problem-solving and cross-functional collaboration.

Responsibilities

• Design, implement, and verify complex ASICs with SystemVerilog.
• Perform synthesis and timing analysis to meet PPA goals.
• Collaborate with hardware/software teams for integration.
• Create thorough design documentation and reports.

Skills

SystemVerilog

RTL design

Synthesis

Timing analysis

High-speed I/O

PCIe knowledge

Front-end chip development (CDC/RDC/LE

Education

BS degree in Electrical/Computer Engineering

Tools

ASIC design tools

Simulation tools

Formal verification tools

Job description

Apple’s Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom SoCs that drive the performance and efficiency of Apple’s products. You will work on cutting‑edge technologies and collaborate with cross‑functional teams to deliver groundbreaking solutions.

Description

Design and Development: Design, implementation, and verification of complex ASICs. Develop RTL using SystemVerilog and perform synthesis.

Verification: Engage with simulation-based and formal verification teams to ensure robust design validation.

Integration and Testing: Collaborate with hardware and software teams to integrate digital designs into complex SoCs.

Timing and Power Analysis: Conduct timing analysis and power optimization to achieve PPA goals.

Documentation and Reporting: Create detailed micro‑architecture and design documentation.

Minimum Qualifications

• Minimum of BS + 10 years relevant industry experience

Preferred Qualifications

• Experience: 8+ years of proven experience in ASIC design, including RTL design and verification. Hands‑on experience with ASIC design tools and methodologies is essential.
• Technical Skills: Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis.
• Problem‑Solving: Strong analytical and problem‑solving skills.
• Collaboration: Excellent communication and teamwork skills, work effectively in cross‑functional teams.
• Attention to Detail: Meticulous attention to detail and a commitment to delivering high‑quality designs.
• Experience with high‑speed I/O design and protocols. Knowledge of PCIe is a plus.
• Familiarity with custom ASIC design and FPGA prototyping.
• Hands on experience in all aspects of front‑end chip development process (e.g., CDC/RDC, LINT, LEC, etc.).
• Knowledge of low‑power design techniques and power optimization strategies.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.