ASIC Design and Integration Engineer - Silicon Security

Socket.dev; Cupertino (CA); On-site; USD 190,000 - 240,000; Full time

Job summary

Apple's Silicon Security team is seeking an ASIC Design Engineer to build secure subsystems for the Apple SoC, defending against side-channel attacks and protecting data across devices.

Responsibilities include architecting security features, integrating IPs, and driving RTL-to-netlist quality with timing and power efficiency. Familiarity with cryptography and AMBA protocols is beneficial.

Qualifications

• BS in Electrical Engineering, Computer Engineering or a relevant field with 0 years of experience.
• Experience with RTL design, Verilog or SystemVerilog is preferred.

Responsibilities

• Architect and design security features for secure subsystems.
• Integrate security IPs and ensure timing, performance, and security.
• Resolve integration issues across IP blocks and coordinate with IP owners.
• Drive front-end quality flows from RTL to netlist, including lint, CDC/RDC analysis, UPF, timing, and synthesis.
• Leverage AI-assisted tools to enhance design quality.

Skills

RTL design

Verilog

SystemVerilog

CDC analysis

RDC analysis

UPF

timing closure

cryptography

AMBA protocols

hardware security

Education

BS in Electrical Engineering or related field

Job description

Apple's Silicon Security team is looking for a driven ASIC Design Engineer to build the secure subsystems that protect the entire Apple SoC. In this role, you will design the state-of-the-art hardware defenses that prevent complex side channel attacks and ensure the integrity of our customers' most sensitive data across Apple's product line. Our work spans cryptographic engines, side channel attack monitors, data protection logics etc that make Apple devices the most secure consumer electronics in the world.

Description

• Architecting and designing state-of-the-art security features, working closely with Platform Architecture, Design Verification to deliver high performance, area and power efficient RTL Blocks on time
• Integrating security IPs into secure subsystem and ensuring timing, performance and security requirements are met.
• Resolving integration issues across multiple IP blocks and coordinating with IP owners on interface and functionality concerns
• Driving front-end quality flows from RTL to netlist, including hands-on work with Lint, CDC/RDC analysis, UPF development, timing, and Synthesis.
• Leveraging AI-assisted tools to enhance design quality and productivity.

Minimum Qualifications

• BS in Electrical Engineering, Computer Engineering or a relevant field and 0 years of experience

Preferred Qualifications

• RTL design experience using Verilog or SystemVerilog.
• Experience with CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis and verification.
• Familiarity with low-power design techniques and UPF (Unified Power Format).
• Solid understanding of digital design fundamentals including synthesis, timing closure, and design for testability.
• Background in cryptography and cryptographic algorithm implementation.
• Experience with hardware security concepts including key management, physical attack and countermeasures.
• Experience with clock and reset architecture at the subsystem level
• Strong knowledge of AMBA bus protocols (AXI, AHB, APB).