RTL-to-GDS Physical Design Engineer for High-Speed IP

TPI Global Solutions; Santa Clara (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

TPI Global Solutions in Santa Clara, CA is seeking a Physical Design Engineer to take RTL to GDS with synthesis, Place & Route, timing, and physical verification. The role focuses on automation-driven flows for high-speed datapath IP, floor planning, clock tree synthesis, clock gating, and signoff for large IP deliveries.

Strong Verilog and EDA tool expertise preferred. Ideal candidates will have experience with ICC2, Fusion Compiler, Calibre, and PrimeTime, plus a Master’s or Bachelor’s degree

Qualifications

• Experience with automated synthesis and timing-driven P&R for high-speed datapath and control logic.
• Proficient with floor planning, timing, electrical checks, and IP signoff processes.
• Strong background in digital circuit techniques and low-power/high-speed design principles.

Responsibilities

• Lead RTL-to-GDS design flow including synthesis, P&R, timing, and physical verification.
• Support floor planning, establishing design methodology, checks for logic equivalence, and final IP signoff for large IP delivery.

Skills

Automated synthesis

Timing-driven P&R

Verilog

ICC2

Fusion Compiler

Calibre

PrimeTime

Clock tree synthesis

Clock gating

Scan stitching

Education

Master's degree in EE/CS

Bachelor's degree in EE/CS

5+ years relevant experience

Tools

ICC2

Fusion Compiler

Calibre

PrimeTime

Job description

TPI Global Solutions in Santa Clara, CA is seeking a Physical Design Engineer to take RTL to GDS with synthesis, Place & Route, timing, and physical verification. The role focuses on automation-driven flows for high-speed datapath IP, floor planning, clock tree synthesis, clock gating, and signoff for large IP deliveries.

Strong Verilog and EDA tool expertise preferred. Ideal candidates will have experience with ICC2, Fusion Compiler, Calibre, and PrimeTime, plus a Master’s or Bachelor’s degree