Physical Design Engineer

TPI Global Solutions; Santa Clara (CA); Presencial; USD 140 000 - 210 000; Tempo integral

Resumo da oferta

TPI Global Solutions in Santa Clara, CA is seeking a Physical Design Engineer to take RTL to GDS with synthesis, Place & Route, timing, and physical verification. The role focuses on automation-driven flows for high-speed datapath IP, floor planning, clock tree synthesis, clock gating, and signoff for large IP deliveries.

Strong Verilog and EDA tool expertise preferred. Ideal candidates will have experience with ICC2, Fusion Compiler, Calibre, and PrimeTime, plus a Master’s or Bachelor’s degree

Qualificações

• Experience with automated synthesis and timing-driven P&R for high-speed datapath and control logic.
• Proficient with floor planning, timing, electrical checks, and IP signoff processes.
• Strong background in digital circuit techniques and low-power/high-speed design principles.

Responsabilidades

• Lead RTL-to-GDS design flow including synthesis, P&R, timing, and physical verification.
• Support floor planning, establishing design methodology, checks for logic equivalence, and final IP signoff for large IP delivery.

Conhecimentos

Automated synthesis

Timing-driven P&R

Verilog

ICC2

Fusion Compiler

Calibre

PrimeTime

Clock tree synthesis

Clock gating

Scan stitching

Formação académica

Master's degree in EE/CS

Bachelor's degree in EE/CS

5+ years relevant experience

Ferramentas

ICC2

Fusion Compiler

Calibre

PrimeTime

Descrição da oferta de emprego

• This is a Physical Design Engineering role that will require to take the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification.

Responsibilities:

• This engineer will work on leading edge technology nodes designs. This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• You will also support floor planning, establishing design methodology, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

Preferred skilled sets:

• Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications. Mainly in ICC2, fusion compiler, calibre and Prime Time.
• Experience in automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications.

Education:

• Major in EE, CS or related, master's degree with 3+ years or Bachelor with 5+ years working experience, preferably with high designs or other high-performance IP design.