CPU Micro-Architect / RTL (Lead & IC Engineers)

NUVACORE; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

NUVACORE in Austin is looking for a CPU Micro-Architect/RTL Engineer to work on groundbreaking high-performance CPU designs. You will be part of a dynamic team developing specifications and RTL targeting exceptional power, performance, and area.

Requirements include 15+ years of experience for leads and expertise in Verilog, RISC-V, ARM64, or x86. The position supports remote hires within US/Canada, although preference is for local candidates.

Qualifications

• 15+ years experience for leads, 7+ years for ICs in CPU design.
• Experience coding in Verilog and debugging solidly.
• Understanding of logic and physical design impacts.

Responsibilities

• Develop micro-architecture specifications for CPUs.
• Refine RTL design targeting power, performance, and timing goals.
• Assist verification team in CPU verification phases.

Skills

Verilog coding

CPU design

High-performance design techniques

C/C++ programming

Education

BS or MS in relevant field

Job description

We have new roles being added daily.In the meantime, if you see a way to contribute to building high-performance CPUs and work with world-class teams, please send us your resume.

Full-time · US / Canada IC + Tech Lead

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As engineers within the CPU team and as leads of CPU units (fetch, decode/rename, scalar execute, fp/vector execute, load/store, memory management/TLB, prefetching, debug/trace, system/IO, and multi-level cache subsystem), you will be writing specifications and develop RTL for the CPU which targets and delivers industry leading power, performance, and area.

THE ROLE

As a CPU Micro-Architect/RTL Engineer, you will participate in the following:

• Micro-architecture development and specification - starting from a performance driven design strategy, you will work with our performance modeling team and study early micro-architectures and converge on a design captured in a detailed specification. Critical understanding of the various pipelines and intra-unit communication will be necessary to build a clean, yet, performant design.
• RTL design - develop and refine RTL which targets the power, performance, area and timing goals. A solid understanding of the modern verilog standards is a plus, enabling you to write RTL which is flexible and robust, configurable, and scalable.
• Verification - assist the verification team in all forms of CPU verification used, such as test bench development, formal methods, and simulation/emulation for formal verification
• Performance exploration and correlation - explore high-performance strategies and work with the performance architecture and verification team to verify that the RTL meets targeted performance.
• Physical design - work with the PD engineering team to implement and verify the physical design meets the goals. Be able to iterate and refine the RTL design. Incorporate improvements for timing, power, area, DFT, and reliability.

REQUIREMENTS — MUST HAVE

• BS or MS with 15+ (leads) and 7+ (ICs) years experience in high-performance, low-power CPU design
• Experience with coding in Verilog, debugging, simulation, ideal experience in driving modern AI engines to assist in RTL coding
• Solid understanding in logic and physical design and the impacts on timing, power, and area
• Experience with RISC-V or ARM64 or x86 ISA and their impacts on CPU micro-architectural choices

REQUIREMENTS — nice to HAVE

• Expertise in one or more of the following areas: instruction fetch, branch prediction; instruction decoding, scheduling and register renaming; out-of-order execution; integer and floating point execution; load/store execution; prefetching; cache and memory subsystems; translation and memory management; memory coherence and ordering; power and thermal management; and, clocking / reset design
• Strong background in low power microarchitecture and high-performance design techniques, with a proven track record of execution on multiple CPU programs and productions
• Experience in C, C++, and other languages such as Perl or Python
• Strong preference for being located at one of the main company offices in Austin, San Jose, or Toronto. Remote hires still within US/Canada are considered on a case by case basis and must be willing to do occasional business travel.