Senior CPU RTL Architect (RISC-V)

Tenstorrent; California (MO); Hybrid; USD 100,000 - 500,000; Full time

Benefits offered by this job

Highly competitive compensation package

Benefits and equal opportunity employer

Job summary

Tenstorrent is seeking a talented engineer to join their CPU design team to define and implement RTL for high-performance RISC-V CPUs. In this hybrid role, you will collaborate with various teams to ensure a functional and efficient design.

The ideal candidate will have expertise in CPU microarchitecture and RTL coding. Compensation ranges from $100k to $500k, depending on experience and skills. Join a passionate team revolutionizing AI technology!

Qualifications

• Experience in CPU microarchitecture with expertise in Rename and Scheduler.
• Skilled in RTL coding and familiar with industry-standard tools.
• Proficient in debugging RTL/logic in various design environments.

Responsibilities

• Define and implement RTL for high-performance RISC-V CPUs.
• Collaborate with DV, PD, and performance teams.
• Optimize power, performance, and area for RTL designs.

Skills

CPU microarchitecture

RTL coding (Verilog/VHDL)

Debugging RTL/logic

Microarchitecture definition

Tools

Simulation tools

Synthesis tools

Power analysis tools

Job description

Tenstorrent is seeking a talented engineer to join their CPU design team to define and implement RTL for high-performance RISC-V CPUs. In this hybrid role, you will collaborate with various teams to ensure a functional and efficient design.

The ideal candidate will have expertise in CPU microarchitecture and RTL coding. Compensation ranges from $100k to $500k, depending on experience and skills. Join a passionate team revolutionizing AI technology!