RTL integration Engineer

Broadcom; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Job summary

Broadcom is seeking a highly capable hardware verification engineer in San Jose to perform IP integration and test/debug at the SoC level. The role includes RTL design, linting, and comprehensive CDC/RDC analysis for RTL and gate-level designs, with synthesis, palladium modeling, and STA support as part of the responsibilities.

The candidate should have deep experience with UVM, SystemVerilog, GLS, and advanced simulation tools (NCSim, VCS), and excel in a fast-paced, globally distributed team.

Qualifications

• Bachelor's degree plus 12+ years related experience.
• Strong understanding of UVM and SystemVerilog.
• Experience with gate-level simulation (GLS).
• CDC analysis for RTL and gate-level designs.
• Familiarity with CDC and SDF simulations; debugging expertise.
• Experience with NCSim and VCS.

Responsibilities

• IP integration and IP test/debug mode verification at the SoC level.
• Create RTL designs, perform linting, and execute CDC/RDC analysis for RTL and gates.
• Handle synthesis, Palladium modeling, and STA support; perform debugging.

Skills

UVM

SystemVerilog

debugging

independent worker

global team

learning new tools

excellent communication

Education

Bachelor's degree

Tools

NCSim

VCS

Job description

USA-CA San Jose Innovation Drive

Full time

R026729

Job Description:

The candidate will be required to perform IP integration and IP test/debug mode verification at the SoC level. This role involves creating RTL designs, performing linting, and executing CDC and RDC analysis for both RTL and gates. Additionally, the candidate will handle synthesis, palladium modeling, and STA support. Strong debugging skills are highly required.

Requirements:

• Extensive knowledge of implementation, synthesis, and timing issues.
• Strong understanding of UVM and SystemVerilog is required.
• Deep familiarity with zero-delay and SDF simulations, including the ability to debug failures effectively.
• Proven experience in gate-level simulation (GLS).
• Familiarity with Clock Domain Crossing (CDC) analysis for both RTL and gate-level designs.
• Highly desirable experience with simulation tools such as NCSim and VCS.
• Ability to work independently with minimal supervision.
• Experience working within a global team and a dynamic environment.
• Strong ability to quickly learn and adapt to new tools and methodologies.
• Excellent communication skills are a must.

Education and Experience:

• Bachelors and 12+ years of related experience;

Compensation and Benefits

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in Broadcom!

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