R&D Engineer IC Design 4

Broadcom; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Medical, dental and vision

401K with match

ESPP

EAP

Paid holidays

Paid time off

Job summary

Broadcom seeks an experienced engineer to lead frontend design and verification for core ASIC blocks. You will architect, design, synthesize and constrain RTL, then verify with simulation and formal methods while analyzing timing across high-frequency process nodes.

The role requires strong RTL knowledge, system-level thinking, and collaboration across geographies. Broadcom offers a robust compensation package and comprehensive benefits.

Qualifications

• BS/MS in Electrical or Computer Engineering or equivalent.
• 8+ years of related ASIC/standard product implementation experience.
• Experience with RTL synthesis, timing analysis and closure.
• Proficiency with design tools: TCL/Perl scripting, Synopsys Design Compiler or Cadence RTL compiler, Primetime, Liberty LIB models, Formality, Conformal, Spyglass, power analysis, DFT/scan, SVN/Git.

Responsibilities

• Front end design and verification for core blocks.
• Define architecture, logic design, synthesis and constraints.
• Verify using simulation, formal verification, and timing analysis.
• Debug designs with Verilog and understand full ASIC design flow.

Skills

RTL design

Timing analysis

Verilog/VHDL

Formal verification

TCL/Perl scripting

Synthesis flow

Education

BSEE / BSCE

MS in related field

Tools

Design Compiler

RTL Compiler

Primetime

Liberty LIB models

Synopsys Formality

Cadence Conformal

SpyGlass

SVN / Git

Job description

USA-CA San Jose Innovation Drive

USA-TX-Austin - River Place B7

Full time

R024801

Job Description

You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture definition, logic design, synthesis, constraint development; design verification through simulation, formal verification, along with analysis of timing from the physical implementation. You will design logic blocks from systems requirements documents and will simulate and debug designs with Verilog simulation. Familiarity with entire ASIC design and implementation flow.

• Ability to work independently as part of a large team spanning multiple geographies.
• Education: BS/MS in Electrical or Computer Engineering or equivalent
• Bachelors and 8+ years of related experience; or Masters degree and 6+ years of related experience
• Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing analysis / closure.
• Requires proficiency with the following design tools / flows:
  • TCL/Perl scripting
  • Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler
  • Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries
  • Understanding of liberty LIB models for timing
  • Formal verification (Synopsys Formality / Cadence Conformal)
  • Spyglass Lint
  • Power analysis of RTL and gate level netlists
  • Familiarity with DFT (design for test) and scan methodology
  • Version control (svn, git, etc)

Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.

We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.

We will also consider qualified applicants with arrest and conviction records consistent with local law.

Welcome! Thank you for your interest in Broadcom!

We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

For more information please visit our video library (http://www.broadcom.com/videos) and check out our Connected by Broadcom (https://www.broadcom.com/support/resources/video-webinar-library?channel=5c9658f7c1d34eca91c6cc16178e5b1b&video=7d72b04ea50046a394e682fab640ce20) series.

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