RTL Engineer for Physical AI Compute SoC

Velaura; Santa Clara (CA); On-site; USD 125,000 - 500,000; Full time

Job summary

Velaura is seeking talented RTL Engineers to help build its next-generation Physical AI SoC. You will design RTL, work with architects, performance modelers, software and verification teams to translate innovative concepts into production silicon.

You will own significant portions of the design, optimize for performance, power, and area, and collaborate across hardware and software to define interfaces and execution flows.

Qualifications

• RTL design for complex digital systems.
• Knowledge of computer architecture and digital design fundamentals.
• Proficient in Verilog/SystemVerilog and modern RTL design methods.
• Understanding of memory systems, interconnects, DMA engines, or accelerators.
• Experience with hardware/software co-design and system-level optimization.
• Strong debugging and problem-solving skills.
• Effective collaboration in multidisciplinary engineering environments.

Responsibilities

• Design, implement, and optimize RTL for key portions of the Velaura SoC.
• Collaborate with architects to develop robust and efficient microarchitectures.
• Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.
• Work with software teams to define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions.
• Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, power-management logic, and other core SoC infrastructure.
• Optimize designs for performance, power, area, scalability, and reliability.
• Partner closely with verification and physical design teams throughout the development cycle.
• Analyze performance bottlenecks and propose architectural and implementation improvements.
• Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.
• Participate in design reviews and contribute to a culture of technical excellence.

Skills

RTL design

Verilog/SystemVerilog

Architecture

HW/SW co-design

Debugging

Collaboration

Tools

FPGA prototyping

Emulation

Performance modeling

Job description

Velaura is seeking talented RTL Engineers to help build its next-generation Physical AI SoC. You will design RTL, work with architects, performance modelers, software and verification teams to translate innovative concepts into production silicon.

You will own significant portions of the design, optimize for performance, power, and area, and collaborate across hardware and software to define interfaces and execution flows.