Senior RTL Engineer — Remote SoC Design & Optimization

Velaura; Santa Clara (CA); On-site; USD 200,000 - 500,000; Full time

Benefits offered by this job

Equity participation

Performance-based incentives

Comprehensive benefits

Job summary

Velaura in Santa Clara, CA is seeking a Senior RTL Engineer to help build our next-generation Physical AI SoC. You will own significant RTL blocks, drive microarchitectural decisions, and collaborate with architects, performance modelers, software, verification, and physical design teams to deliver high-performance hardware.

You will mentor junior engineers, optimize for performance, power, and area, and participate in design reviews.

Qualifications

• 8+ years designing RTL for complex digital systems.
• Strong understanding of computer architecture and digital design fundamentals.
• Expert-level Verilog/SystemVerilog and RTL design methodologies (lint, CDC, synthesis-aware coding).
• Ability to lead and mentor within a multidisciplinary engineering environment.

Responsibilities

• Own the design, implementation, and optimization of RTL for key portions of the SoC.
• Collaborate with architects to develop robust microarchitectures and drive decisions.
• Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.
• Define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions with software teams.
• Mentor junior engineers and lead design reviews to uphold technical excellence.

Skills

RTL design

Verilog/SystemVerilog

Microarchitecture

Performance/power/area tradeoffs

Co-design

Debugging

Leadership

Tools

Lint

CDC

Synthesis

Job description

Velaura in Santa Clara, CA is seeking a Senior RTL Engineer to help build our next-generation Physical AI SoC. You will own significant RTL blocks, drive microarchitectural decisions, and collaborate with architects, performance modelers, software, verification, and physical design teams to deliver high-performance hardware.

You will mentor junior engineers, optimize for performance, power, and area, and participate in design reviews.