RTL Design Lead: Ethernet/PCIe & Memory IPs

Phizenix; Santa Clara (CA); On-site; USD 180,000 - 200,000; Full time

Job summary

Phizenix in Santa Clara is seeking an experienced Digital Design Lead to drive RTL design and verification for next‑generation semiconductor products. You will lead the digital design effort across high‑speed interface and memory IPs, partnering with architecture, verification, and physical design teams to deliver silicon‑ready designs.

Your role includes leading RTL design, owning Ethernet/PCIe controller/PHY design, and integrating memory sub-systems like DDR, HBM, and LPDDR, while optimizing

Qualifications

• Proven RTL design leadership on complex ASIC/SoC projects.
• Hands-on Ethernet/PCIe controller/PHY design experience.
• Experience with DDR, HBM, LPDDR sub-systems.
• FEC knowledge for high-speed SerDes links.
• Strong Verilog/SystemVerilog coding and ASIC flows knowledge.
• Experience with timing closure and low-power/DFT.
• Effective communication and team leadership.

Responsibilities

• Lead RTL design and micro-architecture definition for digital IP blocks from concept through tape-out.
• Own design of Ethernet and/or PCIe controller/PHY digital logic, ensuring compliance with industry specs.
• Design and integrate memory sub-system IP, incl. DDR, HBM, LPDDR controllers and PHYs.
• Implement and optimize FEC logic for high-speed SerDes links.
• Drive design reviews, timing closure, and low-power design practices with cross-functional teams.
• Mentor junior design engineers and coordinate with verification, DFT, and physical design teams.

Skills

RTL Design Lead

Ethernet/PCIe design

Memory Sub-systems

FEC for SerDes

Verilog/SystemVerilog

Timing closure/DFT

Leadership/mentoring

Communication skills

Education

BS or MS in Electrical/Computer Engineering

Tools

ASIC design flows

DFT tooling

Job description

Phizenix in Santa Clara is seeking an experienced Digital Design Lead to drive RTL design and verification for next‑generation semiconductor products. You will lead the digital design effort across high‑speed interface and memory IPs, partnering with architecture, verification, and physical design teams to deliver silicon‑ready designs.

Your role includes leading RTL design, owning Ethernet/PCIe controller/PHY design, and integrating memory sub-systems like DDR, HBM, and LPDDR, while optimizing