RTL Design Lead for High-Speed SoC & Memory IP

PHIZENIX; California (MO); On-site; USD 140,000 - 190,000; Full time

Job summary

PHIZENIX is seeking an experienced Digital Design Lead to drive RTL design and verification for next-generation semiconductor products. The role leads digital design across high-speed interface and memory IPs, partnering with architecture, verification, and physical design teams to deliver silicon-ready designs.

You will mentor design engineers and collaborate with verification, DFT, and physical design teams to meet project schedules, ensuring quality and performance at scale.

Qualifications

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or a related field.
• Hands-on RTL design leadership in complex ASIC/SoC projects.
• Experience with Ethernet and/or PCIe protocol design (controller/PHY).
• Memory sub-systems design involving DDR, HBM, LPDDR controllers/PHYs.
• Understanding of FEC schemes for high-speed SerDes.
• Strong RTL coding with Verilog/SystemVerilog and standard ASIC flows.
• Experience with timing closure, low-power design, and DFT considerations.

Responsibilities

• Lead RTL design and micro-architecture for digital IP blocks from concept to tape-out.
• Own design of Ethernet and/or PCIe controller/PHY digital logic, ensuring spec compliance.
• Design and integrate memory sub-system IP (DDR/HBM/LPDDR controllers & PHYs).
• Implement and optimize FEC logic for high-speed links.
• Drive design reviews, timing closure, and low-power design practices with cross-functional teams.
• Mentor junior engineers and coordinate with verification, DFT, and physical design teams.

Skills

RTL design leadership

Ethernet/PCIe protocol design

Memory sub-systems design

FEC for SerDes

Verilog/SystemVerilog

Timing closure/DFT

Leadership/mentoring

Education

Bachelor's or Master's in Electrical/Computer Engineering

Job description

PHIZENIX is seeking an experienced Digital Design Lead to drive RTL design and verification for next-generation semiconductor products. The role leads digital design across high-speed interface and memory IPs, partnering with architecture, verification, and physical design teams to deliver silicon-ready designs.

You will mentor design engineers and collaborate with verification, DFT, and physical design teams to meet project schedules, ensuring quality and performance at scale.